Erasable programmable read-only memories ("EPROMs") have been known and used in many areas. One prior use of the EPROMs is in programmable logic devices ("PLDs"). A prior PLD typically includes a programmable logic array that may be comprised of a plurality of EPROM cells. In this instance, PLDs are also erasable and can be referred to as erasable programmable logic devices ("EPLDs").
Typically, the logic array includes a plurality of row lines (i.e., word lines) and a plurality of column lines (i.e., bit lines). The PLD also includes a plurality of device inputs, each of which is divided into an inverting input and a non-inverting input and therefore is coupled to a pair of word lines of the logic array. Each column of the memory cells are coupled together to one of the bit lines. The bit lines of the logic array provide outputs of the logic array. These bit line outputs are then sensed by sensing amplifiers to determine the logical values, each of the sensing amplifiers is coupled to each of the bit lines. The product outputs from the sensing amplifiers are then OR'ed to provide a sum of the products.
As discussed above, each of the device inputs of the PLD is divided into an inverting word line input and a non-inverting word line input that are coupled to a pair of the word lines of the logic array. Therefore, at any given time as many as half of the EPROM cells on a bit line may be conducting if all EPROM cells along the bit line are unprogrammed. The speed performance of the PLD is determined by the time required for a plurality of EPROM cells in the logic array to change from a conducting state to a non-conducting state, or vice versa. The transition phase is dependent upon the number of unprogrammed (i.e., erased) EPROM cells selected in a certain column of the array. For example, when a particular memory cell is conducting, the conducting cell effectively places a low voltage on its bit line, whereby a given value of current is drawn through that particular cell. Assuming that each cell draws approximately the same value of current, the amount of current drawn on the bit line will be equivalent to the conduction current of the given cell multiplied by the number of cells that are conducting.
One disadvantage of the prior PLD is that when multiple cells are conducting, a higher current flow occurs on the bit line which results in a higher voltage swing between the "on" state (i.e., logical low output at the bit line and the "off" state (i.e., logical high output at the bit line). The increased voltage swing results in a longer period of time required for the bit line to stabilize to its "on" and "off" states, which ultimately affects the speed performance of the PLD.
One prior solution to solving the problem is shown in FIG. 1. In FIG. 1, a column of memory cells 8 through n are shown, each having its drain coupled to a first bit line 4a and its source to a second bit line 4a. The output of the column at the first bit line 4a is coupled to a sensing amplifier formed by inverters 6 and 7. The second bit line 4b is coupled to ground via a current limiting transistor 5. Transistor 5 has its gate coupled to the output of the first bit line to receive a feedback signal for controlling the current on the bit lines 4a and 4b. A detailed description of this prior solution is disclosed in the U.S. Pat. No. 4,785,423 to Skupnjak et al.
One disadvantage associated with the prior solution is that the current limiting transistor 5 only functions to control the discharge of the bit lines to a higher voltage level at the "on" state so as to present a smaller signal voltage swing. The voltage level at the "off" state, however, is not lowered by the current limiting transistor 5 and the signal swing typically remains in a larger range of 3 volts, which still affects the speed performance of the PLD.
Another disadvantage associated with this prior solution is that transistor 5 needs to be very large in order to perform the current limiting function on the bit lines. The large transistor 5 typically occupies more space in the PLD, which then reduces the integration degree of the PLD. It also capacitively loads the circuit and slows the switching speed.